U.S. Pat. No. 5,300,803 A discloses a non-volatile memory structure having a compilation mechanism of SSI (Source Side Injection). This floating gate flash memory using SSI as the compilation mechanism effectively improves the injection efficiency of compilation, and reduces the power consumption. This flash memory device proposed in this patent was originally a new structure produced to solve the low injection efficiency and high power consumption of the floating gate flash memory device having a compilation mechanism of CHEI (channel hot electron injection).
Referring to FIG. 1, It can be seen from the portion above the double arrow in the diagram of FIG. 1 that, in a device of the original floating gate flash memory structure having a compilation mechanism of CHEI, in order to ensure a high generation rate of channel hot electrons, a high voltage must be applied to the drain. At the same time, in order to ensure a high efficiency of hot electron injection, a high voltage must be applied to the gate. The transverse electric field is decreased as the gate voltage increases. Similarly, the longitudinal electric field is increased as the gate voltage increases. Thus, in the device of the original floating gate flash memory structure having the compilation mechanism of CHEI, the high voltage must be applied to both of the drain and the gate. This leads to the low efficiency of channel hot electron injection and the high current power consumption. Consequently, the high gate voltage and the high drain voltage are in contradiction with each other.
Therefore, this patent (U.S. Pat. No. 5,300,803 A) invents a separately arranged gates flash memory device. As shown in the portion below the double arrow in the diagram of FIG. 1 (it is a schematic principle diagram of an existing floating gate flash memory using SSI as a compilation mechanism), the gate on the left is a control gate, and the gate on the right is a floating gate. The floating gate and the control gate are arranged in a staggered manner in space. A high voltage is applied to the floating gate, a low voltage is applied to the control gate, and a high voltage of 5v is applied to the drain. This can improve the injection efficiency of channel hot electrons, and reduce the current power consumption.
The floating gate flash memory structure of separately arranged gates disclosed in this patent has a problem in that: as a result of the relatively high voltage (5v) being applied to the drain, the width of the depletion layer of the drain which extends to the substrate is relatively large, and the source and the virtual depletion region are easy to come into contact with each other in the case of a high voltage, leading to device punchthrough and failure. This defect is easy to lead to device punchthrough and failure when the device size is reduced to 100 nm. For such a floating gate flash memory, there is no way to perform upgrade of technology node and critical dimension shrink in the process. Therefore, it is necessary to change the structure of this floating gate flash memory device, so that the upgrade of technology node and critical dimension shrink can be performed on it in the process.
At the same time, we will encounter a problem of threshold voltage drift during the dimension shrink of the flash memory. As pointed out in the literature “Modeling of Vth Shift in NAND Flash-Memory Cell Device Considering Crosstalk and Short-Channel Effects” [1], as the critical dimension of the flash memory is gradually decreased to a range of sub-100 nm or less, the short channel effect also appears gradually. This has an effect on the electrical characteristics of the memory device, and causes the threshold voltage thereof to drift to some extent as compared with the case of a long channel, leading to possible readout errors.
The double-gate MOSFET mentioned in the previous literatures is a device structure developed to cope with the short channel effect during the continuous shrink of the transistor dimension. When the channel dimension is reduced to less than 100 nm, due to its large gate-controlled area and strong electrostatic control ability, it is possible to effectively eliminate the short channel effect caused by the small dimension.
Also as described in the literature “Double-Gate Silicon-on-Insulator Transistor with Volume Inversion: A New Device with Greatly Enhanced Performance” [2], the double-gate MOSFET has excellent performance, and can achieve a large subthreshold slope, and a large transconductance and drain current. It is known that, due to the short channel effect, when the MOSFET dimension is reduced, the subthreshold slope will become smaller, leading to the incapability of shutoff of the device and a relatively large leakage current. With the double-gate structure, it is possible to effectively suppress the similar short channel effects, including the hot carrier effect, the threshold voltage drift effect, the DIBL (drain-induced barrier lowering) effect and the like. In summary, the double-gate MOSFET is one of the most powerful candidate device structures in the case in which the critical dimension of the MOSFET goes into sub-20 nm in the future.    [1] Sang-Goo Jung, Keun-Woo Lee, Ki-Seog Kim, Seung-Woo Shin, IEEE Transactions on Electron Devices, Volume: 55 Issue: 4, p. 1020, 2008    [2] Francis Balestra, Sorin Cristoloveanu, Mohcine Benachir, Jean Brini, and Tarek Elewa, IEEE EDL, volume 8, no. 9, p. 410, 1987